Now accepting design teams

Silicon design,
accelerated.

RTL regression in minutes, not days. Same Verilog. Same testbenches. 10–50x faster regressions.

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Why Verion

Chip design has outgrown its tools.

Design complexity doubles every generation. Simulation infrastructure hasn't kept up. Verion closes the gap.

10x – 50x faster

Outperforms CPU simulators on regressions. Ship silicon faster.

Your IP stays yours

Runs on-premise or in your cloud. Design data never leaves your infrastructure.

Full observability

Complete debug traces and coverage metrics. No FPGA black boxes.

Built for

IC & Silicon Startups

Emulator-grade throughput without the massive CapEx. Scale on cloud GPUs.

Fabless Design Teams

Shrink the regression wall. Run more iterations before tape-out.

Hyperscalers

Put idle GPU clusters to work on chip verification between AI training jobs.

How it works

From RTL to results
in three steps.

Compile

Point Verion at your existing Verilog or SystemVerilog. The compiler analyzes your RTL and maps it onto GPU-optimized execution kernels. No rewriting required.

Distribute

Verion partitions your design across available GPUs — on-premise or in the cloud. Testbenches and stimulus run in parallel across thousands of GPU cores.

Simulate

Run cycle-accurate simulation at 10-50x the speed of CPU tools. Get full waveform dumps, code coverage, and debug traces — no compromises.

Product

Drop-in GPU simulation.
No rewrites required.

Verion's compiler maps standard Verilog and SystemVerilog onto GPU clusters automatically. The irregular branching of chip logic is partitioned and parallelized — unlocking throughput that CPU simulators cannot match.

	CPU Sim	FPGA	Verion
Speed	Baseline	Fastest	10x–50x faster
Compile time	Fast	Long	Fast
On-premise	Yes	Yes	Yes
Cloud scaling	Limited	No	Yes
Cost	Low	Very high CapEx	OpEx only

Capabilities

Cycle-accurate simulation

Full-cycle, cycle-accurate execution with multi-GPU scaling.

Fast compile & iterate

Fast compile times, save/restore, and dynamic stimulus reconfiguration.

Coverage built in

Code coverage metrics out of the box. No extra tooling.

Open ecosystem

Open API. Inspect it, build on it, integrate it. No vendor lock-in.

Integration

Works with your existing flow.

Interfaces

DPI, VPI, SCE-MI, UVM

APIs

Python, Rust, C++

Hardware

Nvidia, AMD, Apple Metal

Developer experience

A few lines to launch
a regression.

Native SDKs for Rust, C++, and Python. Load your design, run simulation, extract results — all programmatic.

verion simulator

use verion_simulator::SimulatorBuilder;

fn main() -> anyhow::Result<()> {
    let mut dut = SimulatorBuilder::new()
    .build()?;

    dut.reset();

    dut.poke_signal("a", true)?;
    dut.poke_signal("b", true)?;
    dut.step();

    let sum = dut.peek_signal("sum")?;
    let carry = dut.peek_signal("carry")?;
    println!("sum={}, carry={}", sum, carry);

    dut.sync();

    Ok(())
}

▌

#include "verion.h"
#include <stdio.h>

int main() {
    SimResult res = sim_create();

    res = sim_reset(res.handle);

    sim_poke_signal(res.handle, "a", true);
    sim_poke_signal(res.handle, "b", true);
    res = sim_step(res.handle);

    uint64_t sum, carry;
    sim_peek_signal(res.handle, "sum", &sum);
    sim_peek_signal(res.handle, "carry", &carry);
    printf("sum=%llu, carry=%llu\n", sum, carry);

    sim_dump(res.handle, "dump.vcd");

    return 0;
}

▌

from verion import Simulator

sim = Simulator(
    device_id=0,
)

sim.reset()

sim.poke_signal("a", True)
sim.poke_signal("b", True)
sim.step()

sum_val = sim.peek_signal("sum")
carry = sim.peek_signal("carry")
print(f"sum={sum_val}, carry={carry}")

sim.sync()

▌

Team

We know the verification bottleneck firsthand.

Daniel Kiesewalter

Co-founder

Ex-Sony engineer, AI for chip design. Deep expertise in hardware architecture and machine learning.

Yves Inneichen