Silicon design,
accelerated.
RTL regression in minutes, not days. Same Verilog. Same testbenches. 10–50x faster regressions.
// Team
We know the verification bottleneck firsthand.
DK
Daniel Kiesewalter
Co-founder
Trained LLMs that generate chip designs and surrogate models that outrun simulation at SonyAI. Built mythen, the fastes-accelerating race-car at AM. Designed the fastest electro-optic modulators at Polariton.
LinkedIn YI
Yves Ineichen
Co-founder
ACM Gordon Bell Prize winner. Expert in high-performance computing and GPU-accelerated systems.
LinkedIn